Modeling of subsurface leakage current in low V-TH short channel MOSFET at accumulation bias

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Title: Modeling of subsurface leakage current in low V-TH short channel MOSFET at accumulation bias
Related: IEEE transactions on electron devices, Vol. 63, No. 5, (2016), p.1840-1845
DOI: 10.1109/TED.2016.2544818
Publisher: IEEE
Date: 2016
Author/Creator: Lin, Yen-Kai
Author/Creator: Khandelwal, Sourabh
Author/Creator: Medury, Aditya Sankar
Author/Creator: Agarwal, Harshit
Author/Creator: Chang, Huan-Lin
Author/Creator: Chauhan, Yogesh Singh
Author/Creator: Hu, Chenming
Description: We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source-drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage (VDS), gate-to-source voltage (VGS), gate length (LG), substrate doping concentration (Nsub), and temperature (T) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data.
Description: 6 page(s)
Subject Keyword: BSIM6
Subject Keyword: leakage
Subject Keyword: modeling
Subject Keyword: short channel
Subject Keyword: subsurface
Subject Keyword: zero-VTH MOSFET
Resource Type: journal article
Organisation: Macquarie University. Department of Engineering

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