Please use this identifier to cite or link to this item: http://hdl.handle.net/1959.14/188867
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- Title
- A 3-5 GHz LNA in 0.25µm SOI CMOS process for implantable WBANs
- Related
- IEEE International Midwest Symposium on Circuits and Systems (55th : 2012) (5 - 8 August 2012 : Boise, Idaho)
- Related
- IEEE International Midwest Symposium on Circuits and Systems : MWSCAS 2012 : proceedings : Boise, Idaho, 5 -8 August 2012, p.766-769
- DOI
- 10.1109/MWSCAS.2012.6292133
- Publisher
- Piscataway, N.J : IEEE
- Date
- 2012
- Author/Creator
- Iji, Ayobami
- Author/Creator
- Zhu, Xi
- Author/Creator
- Heimlich, Michael
- Description
- A low-voltage, low-power single-ended LNA is implemented in a 0.25µm SOI CMOS technology. A theoretical basis for the design is used to develop design constraints in conjunction with a layout-aware design flow providing early insight into parasitic effects. The SOI CMOS LNA has a post-layout simulated noise figure of less than 3 dB; input IP3 of −10 dBm and small-signal gain of 19.2 dB within the 3–5 GHz band. Total current consumption is 5.2 mA from 1.5 V supply voltage. The LNA can also operate under a 1V supply voltage with relatively small linear performance degradation. The chip area is 0.89 mm². Due to the high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, the SOI CMOS technology offers significant performance improvements for LNAs, which makes the designed LNA well suitable for implantable WBANs.
- Description
- 4 page(s)
- Resource Type
- conference paper
- Organisation
- Macquarie University. Dept. of Electronic Engineering
- Identifier
- http://hdl.handle.net/1959.14/188867
- Identifier
- ISBN:9781467325264
- Identifier
- ISSN:1548-3746
- Identifier
- mq_res-ext-ieee20120928343-1
- Language
- eng
- Reviewed
