The intermodulation performance of an FET in the common-source configuration is dependent on the impedance presented to its gate and drain terminals, not only at fundamental, but also at harmonic and baseband frequencies. At baseband frequencies, these terminating impedances are usually determined by the bias networks, which may have varying impedance over the frequencies involved. This can give rise to asymmetry in two-tone intermodulation levels, and changing intermodulation levels with tone spacing, as previous studies have shown. In this paper, an FET is analyzed to gain an understanding, useful to the circuit designer, of the contributing mechanisms, and to enable the prediction of bias points and the design of networks that can minimize or maximize these effects. Compact formulas are given to facilitate this. An amplifier was tested, showing good agreement between the theoretical and measured results.
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